Hello!
I've typed a Makefile...but it doesn't work!

Here there's the new Makefile:

CC = gcc

STD0 = -D__KERNEL__ -I/usr/src/linux-2.4.28/include -Wall -Wstrict-prototypes -Wno-trigra
phs -O2 -fno-strict-aliasing -fno-common -fomit-frame-pointer -pipe -mpreferred-stack-bou
ndary=2 -march=i686 -DMODULE -nostdinc -iwithprefix include -DKBUILD_BASENAME

STD1 = -DEXPORT_SYMTAB


primo.o: primo.c
@echo "creazione primo.o"
$(CC) -c $(STD0)=primo $(STD1) primo.c -o primo.o



secondo.o: secondo.c
@echo "creazione secondo.o"
$(CC) -c $(STD0)=secondo secondo.c -o secondo.o

clean:
@rm *.o

The problem is that when I type make, it doesn't call the @echo and the second $(CC). Instead make clean works, why?

Does anyone could help me? Thanks to all...lucs

I would add an "ALL = primo.o second.o" at the top of the file. And before the primo.o and second.o sections add an "all: $(ALL)" in there.

Thank you very much...finally it works, but I've a question: why do I have to insert two all label? Is this a gcc bugs...it should work with an only all label!! lucs

Well I suppose you could do all: primo.o second.o instead of that but generally I do it that way.. who knows why though, I've been doing it for years.