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Old 11-19-2008, 12:28 PM   #1
fardad
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x86_64 stack pointer and offset register


Hi --

I am trying to access the stack using "SS:RSP". I know in 32bit arch we need to point to an address which is a combination of SS:SP
(SS * 0x10 + SP ). SP here is the first 16 significant bit if ESP.

how does this work for 64 architecture? is it still same as 32 bit architecture?

I guess my question is if I know SS and RSP, how could I access exact address the combination of these two register point to?

thanks
Fardad
 
Old 11-20-2008, 07:41 AM   #2
johnsfine
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Quote:
Originally Posted by fardad View Post
I am trying to access the stack using "SS:RSP". I know in 32bit arch we need to point to an address which is a combination of SS:SP
In 32bit arch you can have a mode in which SS:ESP is a different location than DS:ESP, but Linux and Windows don't do that.

In Linux and Windows, an address on the stack is just an ordinary address.

Quote:
(SS * 0x10 + SP ). SP here is the first 16 significant bit if ESP.
(SS * 0x10 + SP ) is the addressing system in 16bit real mode. Even in 16bit Windows it didn't work that way.

Quote:
how does this work for 64 architecture? is it still same as 32 bit architecture?
Segment registers in 64 bit mode retain only a trivial fragment of the meaning they had in 32 bit mode. I think SS has zero function in 64 bit mode.

Quote:
I guess my question is if I know SS and RSP, how could I access exact address the combination of these two register point to?
The exact virtual address is the value in RSP.

The translation of virtual address to physical address is very similar in 64 bit mode to 32 bit mode. The translation from segment:offset to virtual address is not. In 32bit mode, ordinary OS's trivialize the translation from segment:offset to virtual address by having zero as the base value in the descriptor of most segment registers. In 64bit mode, the hardware design trivializes that translation (no matter what the OS sets up for descriptors SS:RSP is the same address as DS:RSP).

Last edited by johnsfine; 11-20-2008 at 07:48 AM.
 
Old 11-21-2008, 04:28 PM   #3
fardad
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Thank you so much for your respond.

The reason I ask my earlier question is following:

I am trying to create a Copy On Write situation by having two process write to a page that is marked as private. I know upon a COW, a page_fault gets generated and CPU depend s on Current Privilege Level does following:

if CPL == 0x3 (executing in user mode)

0) pushes SS and ESP
1) push EFLAG
2) push CS
3) push EIP
4) push error-code
5) jump to page_fault service-routine (handler)


basicaly if a fault has happened, cpu loads CS and EIP with the logical address of the instruction that caused the exception.


I was hoping to be able to use those registers to access the data at the time a write happened.

any help ?

regards
 
  


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