Question about a makefile
I am trying to modify a makefile which currently is like this:
target: file1 some commands When I type make the makefile checks the timestamp of file1 and if it is newer than the target it executes the commands. What I want to do is to execute a few shell commands first which will update file1 or leave it the same. If file1 is updated and only then I want to run the commands of target1. Something like this: target2: if condition then touch file1 target1: file1 some commands I've played with target dependencies, phony targets but I either end up with infinite loop in the makefile or I can't execute the commands of target2 before those of target1. I don't know if I was clear enough... Does anyone have any solution? |
I'm not clear why you cannot put the conditional directly into the command sequence for target1, but if you can't, you can use either multiple makefiles or recursion to achieve this:
Code:
target2: The reason you can't do it with simple dependencies is that you are changing the dependencies after the make has evaluated them. |
as neon shows you can have as many commands as you like
remember the blanks to start the lines are TABS. |
First of all thank you both for your replies.
The original problem I was trying to solve was the following. I have a makefile like this: Code:
ALL_FILES = $(DIR)*.txt I came up to a code like the one in my first post but I'm not sure if I am in the right way or if there is any other solution. neonsignal as you say my problem is that I am changing the dependencies after the make has evaluated them. |
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