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problem in finding path of sourcefiles in makefile

hi guys im trying to write a makefile which contains :two cpp files and two header files.
now i've put cppfiles in a folder called source whose path is: /root/workspace/source

and header files in a folder called header whose path is:
/root/workspace/makedemo/header

my makefile is in the path:/root/workspace/makedemo

my makefile was like this:

Code:

HEADERS = $(shell /root/workspace/makedemo/header ls *.h)

SOURCES = $(shell /root/workspace/source ls *.cpp)



COMPILERFLAGS = -W -Wall

DEBUGFLAGS = -g

CPPCOMPILER = g++



INCLUDES = -I.





OBJS = $(SOURCES:.cpp=.o)



BINARY = output



all: $(BINARY)



$(BINARY): $(OBJS)

        $(CPPCOMPILER) $(COMPILERFLAGS) $(INCLUDES) -o $(BINARY) $(OBJS)

depend:

        makedepend -f- -- $(SOURCES) > .depend_file

clean:

        rm -rf *.o .depend_file $(BINARY) *~



#DO NOT DELETE

im sure that i've given the correct path but it is showing errors like this:

[root@localhost makedemo]# make
/bin/sh: /root/workspace/source: is a directory
/bin/sh: /root/workspace/source: is a directory
g++ -W -Wall -I. -o output
g++: no input files
make: *** [output] Error 1

any help appreciated...

Quote:

Originally Posted by karthik.c (Post 3474154)

Code:

HEADERS = $(shell /root/workspace/makedemo/header ls *.h)

SOURCES = $(shell /root/workspace/source ls *.cpp)



COMPILERFLAGS = -W -Wall

DEBUGFLAGS = -g

CPPCOMPILER = g++



INCLUDES = -I.





OBJS = $(SOURCES:.cpp=.o)



BINARY = output



all: $(BINARY)



$(BINARY): $(OBJS)

        $(CPPCOMPILER) $(COMPILERFLAGS) $(INCLUDES) -o $(BINARY) $(OBJS)

depend:

        makedepend -f- -- $(SOURCES) > .depend_file

clean:

        rm -rf *.o .depend_file $(BINARY) *~



#DO NOT DELETE

It tries to run /root/workspace/source as a command (open shell, type name of any directory and see what happens). Either add cd, or use ls with full paths.

hi erv thanks for your response,i did tried ls command after going to the particular directory and its giving me all .h and cpp files.but when i tried to print the value of SOURCES and HEADERS using echo it didnt print anything.im new to the concept of makefile and it would be better if u can say what is the correct way of giving the path of files then??

This should do the trick:

Code:

SOURCES  = $(shell ls /root/workspace/source/*.cpp)



DEBUG    = -g

CXXFLAGS = $(DEBUG) -Wall -ansi -pedantic

INCLUDES = -I/root/workspace/makedemo/header

LDFLAGS  =

LIBS    =

OBJS    = $(SOURCES:.cpp=.o)



BINARY = output



test:

        @echo $(OBJS)



all: $(BINARY)



$(BINARY): $(OBJS)

        $(CXX) $^ $(LDFLAGS) $(LIBS) -o $@



.cpp.o:

        $(CXX) $(CXXFLAGS) $(INCLUDES) -c $<



depend:

        makedepend -f- -- $(SOURCES) > .depend_file



clean:

        $(RM) $(OBJS) .depend_file $(BINARY)



# DO NOT DELETE

P.S. I am not familiar with 'makedepend'; is this a Solaris app?

On Linux, the dependencies can be built similar to the following:

Code:

@$(CXX) -E -MM $(INCLUDES) $(SOURCES) > .depend_file

>>P.S. I am not familiar with 'makedepend'; is this a Solaris app?

im not sure whether it is a solaris app,but it is a dependency tool in linux which creates dependencies using the source file.
you can check out man makedepend