Optimizing assembler code
 

An enormously repetitive routine calls for simple assembler coding to better control optimization and minimize run time. Given a parent C program with a defined array1:
Please look at these subroutine assembler code snippets to address, say, the element at offset 24 of the array. Which code will execute faster (fewer clock ticks),
This:
or this:
Also, do i gain speed performance by defining my array with long rather than char elements, thus achieving better alignment efficiency?
My assembler code then becomes:
or
The target processor, if that's germaine, is an older AMD-K6 500 mHz.

The target processor is germane - the timing will change across processor models. In addition, the timing on a given processor will change based on the state of the cache and the alignment of the assembly (not assembler) instructions and data.

OK, so the alignment of the data is important. Is align 4 sufficient, or is align 16 better?

I don't anticipate any issues with the cache, as the assembly (not assembler) code will run pretty much exclusively for long stretches.

As to processor specifics, can you tell me where i might find out which code may be better for the AMD chip?

The higher the alignment value, the more universal the benefit, and the greater the wasted space. Cache lines vary between 32 and 128 bytes on most processors.

Unless you are running your code in a single process OS and/or on a dedicated CPU, your CPU cache will be invalidated and flushed quite a bit. Optimizing your locality of reference will minimize that.

None of the performance concerns require the use of assembly code; C compilers are quite capable of performing the necessary optimizations, and allow for increased portability.

Intel has a considerable amount of information online on the subject. You can start here. This is another good article.

Thanks for the info, and the links. I ended up doing my own benchmark tests, since i thought my endeavor may be a bit out of the ordinary, and here's what i found:

Due to several factors - the efficient use of registers and boolean logic, and creative loop controls and stack use, the difference between my assembly code and the best i could get from the C compiler was not just percentage points better, but several times faster.

As i suspected, the cache wasn't an issue. At least, running at runlevel 1 was no faster than at runlevel 2 or higher, providing i wasn't actually running something else simultaneously. I think this was due to the small size of my data and code. Align 4 was adequate. In fact, i experienced a significant speed penalty for going to align 32 or higher, probably because then my small array became big enough to require multiple cache pages.

The answer to my original question (if anyone is interested) is that the use of the data registers edi and esi to access data was faster than direct addressing by about 10%

As one might expect it would be...

A direct-address instruction must be fetched and decoded, then loaded into an internal micro-register to be used in the fetch. But if the address is already in one of the main segment/offset registers, it's already prepared.

There is always a tradeoff of "speed vs. space." So yes, you might well find that it will save time to store each byte of the value in a integer or long-integer. Takes eight times the storage but who cares.

Actually, i was arguing that, in this case, i got both speed and size benefits by using align 4 rather than align 32 or 64 or 128. I'm <em>guessing</em> that's because the larger data array required multiple cache pages, thus slowing things down as well as taking more space in memory. Does this run totally against the grain of processor design principles? (Remember that i'm doing this on an older chip - a 500 mHz AMD.)