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Old 02-26-2004, 09:07 AM   #1
eskimo22
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Registered: Feb 2004
Posts: 11

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make with multiple targets


in several of our projects i need to compile
the same software multiple times with different
defines and for different processortypes.
a simple is this one, it has one common source
but 2 different target processors. the second
target also needs a different define.
my first attempt was this:

PROJ = C101
TARG1 = $(PROJ).hex
TARG2 = $(PROJ)_RJ11.hex

.PHONY : all
.PHONY : clean

all : $(TARG1) $(TARG2)


now i need to declare theese variables different for
each target :

for target1:
MCU = atmega8515
DEFS = -DDEV_SPECIFIC='"../$(PROJ)/dev_specific_cmd.c"'

for target2:
MCU = atmega162
DEFS = -DDEV_SPECIFIC='"../$(PROJ)/dev_specific_cmd_rj11.c"'

also i need to clean up all object and library files before
i compile, because i have different processortypes and also
different code activated via #ifdef ... #endif

how can i accomplish that ? i read a lot of make
documentation today, i just seem stuck ;(
 
Old 02-26-2004, 11:42 AM   #2
chewysplace
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Registered: Sep 2003
Distribution: Slackware 10 w/ Kernel 2.6.8
Posts: 176

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PROJ = C101
TARG1 = $(PROJ).hex
TARG2 = $(PROJ)_RJ11.hex
MCU1 = atmega8515
DEFS1 = -DDEV_SPECIFIC='"../$(PROJ)/dev_specific_cmd.c"'
MCU2 = atmega162
DEFS2 = -DDEV_SPECIFIC='"../$(PROJ)/dev_specific_cmd_rj11.c"'

all : clean $(TARG1) $(TARG2)

clean:
-rm $(TARG1) $(TARG2) *.o

$(TARG1) :
gcc targ1.cpp -o $(TARG1) $(MCU1) $(DEFS1)

$(TARG2) :
gcc targ2.cpp -o $(TARG2) $(MCU2) $(DEFS2)
 
  


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