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On any modern computer, interrupts do have a priority, imposed upon them by a chip such as the APIC. This equipment allows multiple devices to share an interrupt-line, and it allows interrupts to be prioritized.
The "first level" interrupt handler should do the minimum amount of work needed to capture the status of the interrupting device (and to quiesce the interrupt). It may assume that it will not be interrupted by an interrupt of equal-or-lower priority; nothing more.
In a multi-CPU system, however, another CPU may well be manipulating that same data structure!
The "second level" interrupt response ... and this includes anything that involves waiting and so-forth ... should be presumed to happen "soon, but not immediately."
Categorically, do not make any assumptions about the order in which things may occur, nor what kind of wall-clock time delays might be experienced. You are obligated to write code that works correctly: "no matter what, and no matter when."
The kernel source-tree is filled with copious example of "code that works." Study it and copy it, without shame.
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