Is GPL applicable to HDL (hardware definition languages)

archShade · 10-15-2010, 06:43 PM

I have recently graduated from uni and during my time there I have developed an interest in HDL, specifically Verilog.

As my current job doesn't lend itself to doing anything in verilog so I decided to keep myself sharp by designing a 32 bit processor that is similar to (but not the same as) the MIPS processor it will certainly be RISC.

While starting work on it I have decided to start a blog detailing what I have done including the source file as I am entering my work into the wide world I think it needs a licence but I am not looking to make any money or even to derive any fame from what I'm doing. Like I said the main reason to do it is to keep me active in using HDLs.

I hope to gain from the blog suggestions for alternative(better) ways to do what I am doing, for people to use what I have done as an example of a medium sized project in verilog and to force me to have some form of documentation on my project.

That's enough self publication to the question.

Is the GPL (either version 2 or 3) applicable to work in HDL as it is not a traditional programming language but shares many of the same features? It certainly does not feel like I should use a CC licence.

I'm not sure this is the correct forum for this question but it seems most applicable.

Thanking you in advanced for your insight.

Sergei Steshenko · 10-15-2010, 06:59 PM

Quote:

Originally Posted by archShade

... HDL ... is not a traditional programming language ...

Why ? I've been working with Verilog for about 20 years now.

archShade · 10-16-2010, 03:45 AM

Programming languages describe what data to send to various parts of the computer and what to do with the resultant data where as HDL defines the structure of hardware.

They share constructs and act in a similar way but do actually do a different job. Although under synthesis HDLs essential do what programming languages do when applied to an FPGA they work differently.

Because they are so similar I would have thought GPL would cover HDLs but not sure (thus asking).

Sergei Steshenko · 10-16-2010, 03:59 AM

Quote:

Originally Posted by archShade

Programming languages describe what data to send to various parts of the computer and what to do with the resultant data where as HDL defines the structure of hardware.

They share constructs and act in a similar way but do actually do a different job. Although under synthesis HDLs essential do what programming languages do when applied to an FPGA they work differently.

Because they are so similar I would have thought GPL would cover HDLs but not sure (thus asking).

No, Verilog doesn't do a different job. Look up "System C" and realize it's C++ with set of special classes in order to be a good enough as HDL.

Verilog is just a (pseudo-parallel) programming language with built-in threads which are called differently - 'always', 'fork .. join', etc.

At Verilog level of detail 'reg' (typically represented in HW by a edge-triggered flip-flop) is no different from a variable in, say, "C".

Verilog's 'pmos' and 'nmos' are funny in a sense they have conductance in one directions - I once used this deficiency to achieve something quite positive and useful.

...

You might be interested to look up

Petri Nets
.

Sergei Steshenko · 10-16-2010, 04:20 AM

To make my point more clear. Suppose you have the following piece of Verilog code:

Code:

reg r;
always(@posedge clk)
  r = i;

It can be represented simplistically by the following C99 code:

Code:

bool clk; // is set by a different thread
bool ___prev_clk = false; // additional variable needed to detect clk transitions
bool r;
bool i; // is set by a different thread

int main()
  {
  for(;;)
    {
    if(clk && !___prev_clk)
      {
      // if we are here, 'posedge' has just happened
      r = i;
      }

    ___prev_clk = clk;
    }
  }

.

I.e. there is nothing special in Verilog - except convenience for the purpose

.

archShade · 10-16-2010, 10:25 AM

In simulation I would agree that verilog works in the same way as programming languages. I write the code pass it though a compiler (iverilog) and run it (using vvp) all this I could do with systemC but verilog is designed to not only run in this simulated way but also when put though software such as Quartus produce files that have full description off electronic layout, so that it can be applied to a FPGA as firmware or used directly in IC production.

When The design is implemented in this way it no longer takes the guise of a pseudo parallel programming language as those gates really are working in parallel.