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Old 03-07-2009, 06:57 AM   #1
karthik.c
LQ Newbie
 
Registered: Mar 2009
Distribution: linux-centos(Red Hat 3.4.6-10)
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Error in Makefile:No rule to make target `g++',needed by... stop


hi guys i tried to create one Makefile which contains 3 cpp files and 1 header file.(main.cpp,hello.cpp,factorial.cpp,functions.h)when i gave make command it showed:

[root@localhost testproject1]# make
g++ -c -o factorial.o factorial.cpp
g++ -c -o hello.o hello.cpp
g++ -c -o main.o main.cpp
make: *** No rule to make target `g++', needed by `output'. Stop.

i've placed Makefile and other 4 files(headers and sources) in the same directory only but still its showing error
my Makefile was like this:


Code:
HEADERS = $(shell ls *.h)
SOURCES = $(shell ls *.cpp)

COMPILERFLAGS = -W -Wall
DEBUGFLAGS = -g
CPPCOMPILER = g++

LFLAGS =
LIBS =

INCLUDES = -I.
#INCLUDES += /usr/include/c++/4.2

OBJS = $(SOURCES:.cpp=.o)

BINARY = output

all: $(BINARY)

$(BINARY): $(OBJS) $(CPPCOMPILER) $(COMPILERFLAGS) $(INCLUDES) -o $(BINARY) $(OBJS) $(LFLAGS) $(LIBS)

depend:
        makedepend -f- -- $(SOURCES) > .depend_file
clean:
        rm -rf *.o .depend_file $(BINARY) *~

#DO NOT DELETE
 
Old 03-07-2009, 07:41 AM   #2
dwhitney67
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Registered: Jun 2006
Location: Maryland
Distribution: Kubuntu, Fedora, RHEL
Posts: 1,523

Rep: Reputation: 332Reputation: 332Reputation: 332Reputation: 332
You have a problem with this statement:
Code:
$(BINARY): $(OBJS) $(CPPCOMPILER) $(COMPILERFLAGS) $(INCLUDES) -o $(BINARY) $(OBJS) $(LFLAGS) $(LIBS)
It should be:
Code:
$(BINARY): $(OBJS)
        $(CPPCOMPILER) -o $(BINARY) $(OBJS) $(LFLAGS) $(LIBS)
You are also missing a rule to build the object file(s):
Code:
.cpp.o:
        $(CXX) $(COMPILERFLAGS) $(INCLUDES) $<
Of course, you can simplify the rule to make your binary:
Code:
$(BINARY): $(OBJS)
        $(CXX) -o $@ $^ $(LFLAGS) $(LIBS)
Typically COMPILERFLAGS are defined as either CFLAGS or CXXFLAGS. There is no need to explicitly state your compiler, using CC or CXX or even CPPCOMPILER. CC and CXX are built-in types known by the make command. You really should only specify these if you are using a compiler other than the default gcc or g++ compiler.

Also, you should avoid using a wildcard when removing files. If you want to remove your object files, use $(OBJS), not *.o. Also, your Makefile should not be used to clean up after your editor. Do that yourself, or just instruct the editor not to create backup files.

Last edited by dwhitney67; 03-07-2009 at 07:42 AM.
 
Old 03-07-2009, 07:49 AM   #3
dwhitney67
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Registered: Jun 2006
Location: Maryland
Distribution: Kubuntu, Fedora, RHEL
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Rep: Reputation: 332Reputation: 332Reputation: 332Reputation: 332
Btw, here's a Makefile template that I often use:
Code:
# Define executable name
BIN = testing

# Define source files
SRCS = Foo.cpp Main.cpp

# Define header file paths
INCPATH = -I./

# Define the -L library path(s)
LDFLAGS =

# Define the -l library name(s)
LIBS =

# Only in special cases should anything be edited below this line
OBJS      = $(CPP_SRCS:.cpp=.o)
CXXFLAGS  = -Wall -ansi -pedantic
DEP_FILE  = .depend


.PHONY = all clean distclean


# Main entry point
#
all: depend $(BIN)


# For linking object file(s) to produce the executable
#
$(BIN): $(OBJS)
	@echo Linking $@
	@$(CXX) $^ $(LDFLAGS) $(LIBS) -o $@


# For compiling source file(s)
#
.cpp.o:
	@echo Compiling $<
	@$(CXX) -c $(CXXFLAGS) $(INCPATH) $<


# For cleaning up the project
#
clean:
	$(RM) $(OBJS)

distclean: clean
	$(RM) $(BIN)
	$(RM) $(DEP_FILE)


# For determining source file dependencies
#
depend: $(DEP_FILE)
	@touch $(DEP_FILE)

$(DEP_FILE):
	@echo Generating dependencies in $@
	@-$(CXX) -E -MM $(CXXFLAGS) $(INCPATH) $(SRCS) >> $(DEP_FILE)

ifeq (,$(findstring clean,$(MAKECMDGOALS)))
ifeq (,$(findstring distclean,$(MAKECMDGOALS)))
-include $(DEP_FILE)
endif
endif
 
Old 03-09-2009, 12:18 AM   #4
karthik.c
LQ Newbie
 
Registered: Mar 2009
Distribution: linux-centos(Red Hat 3.4.6-10)
Posts: 7

Original Poster
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Hi dwhitney67 thanks for your effort, im new to the concept of makefile and im not able to understand codings in the template.Even though i searched for tutorial in google i didnt get any easy material to refer or understand what each and every line means. so do u know any tutorial which explains it clearly??

Last edited by karthik.c; 03-09-2009 at 12:19 AM.
 
Old 03-09-2009, 12:35 AM   #5
tuxdev
Senior Member
 
Registered: Jul 2005
Distribution: Slackware
Posts: 2,014

Rep: Reputation: 115Reputation: 115
You can actually have gcc create dependency files for you, and also do a bit of other make magic so you don't write any implicit targets or commands for targets other than "clean". Here's the Makefile I use:
Code:
CXX = g++
CXXFLAGS = -O3 -g -w -Wall -Wextra -ansi -pedantic -MD
LINK.o = $(LINK.cpp)
.PHONY = all clean

ifeq ($(GPROF),yes)
CXXFLAGS += -pg
endif

ifeq ($(GCOV),yes)
CXXFLAGS += -O0 -DNDEBUG -fno-elide-constructors -fno-inline -fprofile-arcs -ftest-coverage
endif

SRCS = $(wildcard src/*.cpp)

all: foo

foo: $(SRCS:%.cpp:%.o)

clean:
	$(RM) -f foo core gmon.out *.o *.d *.gcno *.gcov *.gcda

-include *.d
 
Old 03-09-2009, 12:55 AM   #6
karthik.c
LQ Newbie
 
Registered: Mar 2009
Distribution: linux-centos(Red Hat 3.4.6-10)
Posts: 7

Original Poster
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hi again,my makefile is working fine when i made some changes in intendations.Earlier my code was like given below and -o(specified in below line) was in black color:

Code:
$(BINARY): $(OBJS) $(CPPCOMPILER) $(COMPILERFLAGS) $(INCLUDES) -o $(BINARY) $(OBJS) $(LFLAGS) $(LIBS)
but then when i changed that line like given below ,-o was highlighted in red color:

Code:
$(BINARY): $(OBJS)
        $(CPPCOMPILER) $(COMPILERFLAGS) $(INCLUDES) -o $(BINARY) $(OBJS) $(LFLAGS) $(LIBS)
now,my makefile is compiling but im not able to understand what went wrong??can anyone please explain me what the above line of code says??

Last edited by karthik.c; 03-09-2009 at 04:21 AM.
 
  


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