Design of a communication protocol over SPI with master/slave switching
I have to implement a communication between two microprocessors using SPI and three GPIOS. The first one is cr16 running uClinux and the second one is arm7 without an OS. The arm7 serves as the main control unit and on the SPI bus there is a flash memory and the cr16 processor - now the problem begins. Arm7 must work as a SPI master for the flash, however cr16 must work as a master too (it does not have support for slave). At first I though I would be able to implement it in userspace using spidev driver, but I was too slow there, so I wrote a simple chardev, which controls the transfers.
Until now I need only to send a messages in the direction from the arm proc. It is done simply - using GPIO1 the arm signals that the SPI bus is free and switches to the slave mode, cr16 claims the bus, generate the clock and chip select, gets data and frees the bus again.
In uClinux an application thread is using blocking ioctl which is waked up by an interrupt on GPIO1.
However now I need also to send a messages from the cr16 to arm. It can be done similarly - cr16 signals there is a message using GPIO2, then the arm signals free bus by GPIO1 and the transfer can be done.
Unfortunately I can't figure out how to correctly deal with this two situations together - I'm waiting on an action on GPIO1 - which signals the message in one direction and in the same time (asynchronously) I need to send the message in another direction and this action also need GPIO1 to know the bus is free...
Can please anyone give me some advice, how to correctly solve this problem? Excuse me if my description is too messy and also the hardware layout is done for now and can't be changed... I'm interested mainly on the solution on cr16 (uClinux) side.