define multiple variable through loop in makefiles
i want to define multiple varibles in a Makefile in a loop..something like :
i have :
FILES = a.pl b.pl
i want to define a varible having the value as mentioned :
test_a = a
test_b = b
i want to do this assignment in Makefile through a loop.
i tried :
$(foreach f, $(FILES), test_$(basename $(f))= $(basename $(f)))
but this doesn't work..when i see the value of test_a ---it shows null..
can anybody help me in doing this ?
thanks in advance,