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Old 11-28-2007, 08:19 AM   #1
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Registered: Nov 2007
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define multiple variable through loop in makefiles


i want to define multiple varibles in a Makefile in a loop..something like :
i have :


i want to define a varible having the value as mentioned :
test_a = a
test_b = b

i want to do this assignment in Makefile through a loop.

i tried :
$(foreach f, $(FILES), test_$(basename $(f))= $(basename $(f)))

but this doesn't work..when i see the value of test_a ---it shows null..

can anybody help me in doing this ?

thanks in advance,
Old 11-28-2007, 09:16 AM   #2
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you can't do it.


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