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Compiling C code using makefile

Hi
I written four C programs each does different function when received message from client
Common thing for all C programs are socket which act as server and execute function in thread.

Now what I feel there are repitition of code.I want to avoid this.
For example Include directory will be there were wrapper is written for socket etc.
Also I want to use makefile

Please show me some example code so that I can use as reference.

I'm not sure what the question is, but here's the manual for GNU make:
http://www.gnu.org/software/make/manual/make.html

Firstly it sort of matters if these four files link to create one image or if you intend to create multiple targets. As HMW notes, read up on Makefiles and begin with rudimentary ones. There are plenty of examples for how to make the most simple of Makefiles.

And a VERY IMPORTANT make file thing you need to know is PUNCTUATION. Note that when you indent you NEED TO USE TABS AND NOT WHITESPACES. I recommend you use a Linux or Unix editor to create your Makefiles and also ensure that the editor is not configured to replace TAB with spaces.

I have a simple legacy Makefile which I refer to all the time for the basics as well as my list of GCC compiler flags that I like to retain and use. They improve my code because they check for lots of warning conditions and thus help me to not create suspect code. I'll be happy to post that example, but I feel you first ought to make a reasonable attempt to show what you've tried.

The best way to create a makefile is to look at some makefiles. Maybe start with the makefiles used to build make. Hopefully they are up to date and correct. Put all your code in one file and remove duplicate code?

Thanks all

@rtmistler I have one makefile
I made directories as Source, Include, Lib
Source :-cpp files where functions are written
Include:-header files for source cpp
Lib:- After compilation .o files should go in this directory

Source,Include,Lib will be common for all 4 programs I mentioned in first post

Apart from that my first main application appdownload.cpp file will be in project directory along with its include.h file.

Code:

CC                = g++

CFLAGS                = -g -c -Wall 

LDFLAGS                = -lpthread

#SOURCES                = server.cpp tcpstream.cpp tcpacceptor.cpp

SOURCES                = appdownload.cpp

INCLUDES        = -I.

OBJECTS                = $(SOURCES:.cpp=.o)

TARGET                = AppDownload



all: $(SOURCES) $(TARGET)



$(TARGET): $(OBJECTS) 

        $(CC) $(LDFLAGS) $(OBJECTS) -o $@



.cpp.o:

        $(CC) $(CFLAGS) $(INCLUDES) $< -o $@



clean:

        rm -rf $(OBJECTS) $(TARGET)

Please guide me from here

I managed to write working makefile

Code:

CC                = g++

CFLAGS                = -g -c -Wall 

LDFLAGS                = -L/usr/local/lib

LDLIBS      = -lcurl -lpthread

#SOURCES                = server.cpp tcpstream.cpp tcpacceptor.cpp

SOURCES                = appdownload.cpp Source/tcpstream.cpp Source/tcpacceptor.cpp Source/tcpconnector.cpp

INCLUDES        = -I. -I Include/

OBJECTS                = $(SOURCES:.cpp=.o)

TARGET                = appdownload



all: $(SOURCES) $(TARGET)



$(TARGET): $(OBJECTS) 

        $(CC) $(LDFLAGS) $(OBJECTS) $(LDLIBS) -o $@



.cpp.o:

        $(CC) $(CFLAGS) $(INCLUDES) $< -o $@



clean:

        rm -rf $(OBJECTS) $(TARGET)

I think it's an excellent effort and in fact there's little you need assistance with.

Here are some added suggestions:

Start the file with #!/bin/sh, it will help you to be able to use shell variables and commands, for instance I declare START to be `pwd` in case I need to move around directories as part of my make flow. Otherwise I think it will assume a shell no matter what anyways, but I prefer to make that a specific declaration.
My CFLAGS add:

Code:

-Wformat=2 -Werror -Wextra -Wswitch-default -Wswitch-enum -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wmissing-noreturn
Rather than declare my sources I declare the objects and a dependency for their compilation, mine is for C versus CPP:

Code:

OBJS= something.o something-else.o .o: %.c $(GCC) $(CFLAGS) $(INCLUDES) $(DFLAGS) -c &< target: $(OBJS) $(GCC) $(OBJS) (LFLAGS) -o $@
The only other minor suggestion is that I use only "rm -f" not "rm -rf" for my clean. I'm doubtful -rf is needed and I'd stay away from recursively removing directories just in case something weird happens and suddenly "Source" gets removed, along with all the underlying code source files.

I think at this point a lot of this are style differences between one programmer versus another.

What I do is add incrementally new ideas as I see them in other examples or develop them when I need too.

Also do not overlook handy tools like Automake.

If you use these tools to discover dependencies and to construct your makefiles, it is much easier to be certain that your makefiles remain accurate as the program evolves.

Quote:

Originally Posted by rtmistler (Post 5434471)

Start the file with #!/bin/sh,

I don't think adding a #! to a makefile has any effect. You can set the SHELL make variable to explicitly choose the shell used to execute recipes.

5.3.2 Choosing the Shell