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Old 11-06-2005, 07:28 AM   #1
kenneho
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C programming: Adding new source file to project


I have the source for a large c programming project which I'm going to modify. Naturally, the source comes with a Makefile. However, how do I add new source and header files to the project? I guess the Makefile must be modified, but is there tools out there for automatic modification of the Makefile? It seems rather inefficient having to modify the Makefile manually every time I add a new file to the project.
 
Old 11-06-2005, 07:50 AM   #2
Andrew Benton
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Read about autotools online http://sources.redhat.com/autobook/a...l#SEC_Contents or download a copy http://sources.redhat.com/autobook/autobook-1.4.tar.gz
 
Old 11-06-2005, 08:54 AM   #3
kenneho
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I took a glance at it, and it seems like a full days work just reading it. Could you give me an hint on which sections to read - I'm guessing not all of the sections are relevant for my project. I allready have a makefile, and just need to find a smart way of including new source files.
 
Old 11-07-2005, 12:37 AM   #4
Wim Sturkenboom
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The following is a (modified) example from John Goerzen's The Linux progrmming Bible.
Code:
# Lines starting with the pound sign are comments.
#
# These are the two options that may need tweaking

EXECUTABLE = scosch
LINKCC = $(CC)

# You can modify the below as well, but probably
# won't need to.
#

# CC is for the name of the C compiler. CPPFLAGS denotes pre-processor
# flags, such as -I options. CFLAGS denotes flags for the C compiler.
# CXXFLAGS denotes flags for the C++ compiler. You may add additional
# settings here, such as PFLAGS, if you are using other languages such
# as Pascal.

CPPFLAGS = 

LDFLAGS = -lpthread -lm

CC = gcc
#CFLAGS = -Wall -O2 -ggdb3	# debugging
CFLAGS = -Wall -O2		# normal 

CXX = g++
CXXFLAGS = $(CFLAGS)


SRCS := $(wildcard *.c) $(wildcard *.cc) $(wildcard *.C)
OBJS := $(patsubst %.c,%.o,$(wildcard *.c)) \
        $(patsubst %.cc,%.o,$(wildcard *.cc)) \
        $(patsubst %.C,%.o,$(wildcard *.C))
DEPS := $(patsubst %.o,%.d,$(OBJS))

# "all" is the default target. Simply make it point to myprogram.

all: $(EXECUTABLE)

# Define the components of the program, and how to link them together.
# These components are defined as dependencies; that is, they must be
# made up-to-date before the code is linked.

$(EXECUTABLE): $(DEPS) $(OBJS)
	$(LINKCC) $(LDFLAGS) -o $(EXECUTABLE) $(OBJS)

# Specify that the dependency files depend on the C source files.

%.d: %.c
	$(CC) -M $(CPPFLAGS) $< > $@
	$(CC) -M $(CPPFLAGS) $< | sed s/\\.o/.d/ >> $@

%.d: %.cc
	$(CXX) -M $(CPPFLAGS) $< > $@
	$(CXX) -M $(CPPFLAGS) $< | sed s/\\.o/.d/ >> $@

%.d: %.C
	$(CXX) -M $(CPPFLAGS) $< > $@
	$(CXX) -M $(CPPFLAGS) $< | sed s/\\.o/.d/ >> $@

# Specify that all .o files depend on .c files, and indicate how
# the .c files are converted (compiled) to the .o files.

clean:
	-rm $(OBJS) $(DEPS) *~
cleanall:
	-rm $(OBJS) $(EXECUTABLE) $(DEPS) *~

tar:
	tar -cf scosch.tar *.c *.h *.cfg Makefile
	@echo "scosch.tar created"

explain:
	@echo "The following information represents your program:"
	@echo "Final executable name: $(EXECUTABLE)"
	@echo "Source files:     $(SRCS)"
	@echo "Object files:     $(OBJS)"
	@echo "Dependency files: $(DEPS)"

depend: $(DEPS)
	@echo "Dependencies are now up-to-date."

-include $(DEPS)
It automatically picks up new C-files and creates/checks dependencies. It will work as long as all sourcefiles are in one directory.
The book contains examples as well if you have a project which is split over subdirectories.

Modify the flags and the executable name to your requirements. I've added the tar and might have changed something more (long ago). I'm using it now for approx four years and does what I need it to do.
 
Old 11-07-2005, 11:17 AM   #5
kenneho
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Thanks for the script.


However, this is the case: The project I'm working on contains one makefile per subdirectory. Since I'm modifyin the code in just one of these, I
guess I only need to be concerned with the makefile in that particular directory. I was told that the only thing I needed to do when adding a new source file was to edit the file Makefile.am and the run make. So I did. Not surprisingly, it didn't work. Why is this so? I was told that when make was run, the script in Makefile.am added the new files automatically. What am I doing wrong?

If needed I can paste the contents of Makefile.am.

EDIT: It seems as the syntax is right, that is, the function defined in the new source file is recognized. The error seems to occur when the actual building takes place, not while checking the syntax:
Code:
  ./.libs/libospf.so: undefined reference to `wospf_hello'
But again, how do I solve this?

Last edited by kenneho; 11-07-2005 at 11:34 AM.
 
Old 11-07-2005, 11:20 PM   #6
Wim Sturkenboom
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Sorry, I'm not a makefile specialist (that is why I gave the example without any explanantion)..

I guess that you now have multiple makefiles (one per subdirectory) and one main makefile. So first question is where did you add the source (subdirectory or maindirectory) and which makefile did you modify?
 
Old 11-08-2005, 12:41 AM   #7
sasho
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are you multiple make files generated with a configure script?
 
Old 11-08-2005, 03:26 AM   #8
kenneho
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I figured it out!

I have one makefile per subdirectory, and they were all created by the configuration-script. I'm not sure exactly which of the following
things that made it work: Looking more closely at the make-output I noticed that the script complained about my automake-version. Therefore I
installed version 1.9, as version 1.4 was the version currently installed on my system. I addition I run aclocal, as was suggested somewhere for updating the Makefile.am or something. Anyways, this did the trick, and it now works.
 
Old 11-08-2005, 10:09 AM   #9
bigearsbilly
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not much help but worth considering in the future?

recursive make considered harmful
http://www.pcug.org.au/~millerp/rmch...cons-harm.html
 
  


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