understands a few standard macros. One of those is CFLAGS, and make
will use the value of $CFLAGS as commandline options to the C compiler, gcc
, by default. So, in your shell (assuming bash, here) you can set the CFLAGS variable:
export CFLAGS='-W -Wall -fno-common -Wcast-align -Wredundant-decls -Wbad-function-cast -Wwrite-strings -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -pedantic, -Wparentheses -ansi'
Now, exploiting that make
also knows implicitly how to make an executable from a like-named C source file:
This will run gcc
, with the value of $CFLAGS as commandline arguments, and compile and link yourExecutable.c
into the executable object code. The other most commonly used macro is probably $LDFLAGS, which is passed to the linker. You can also pass the macro definitions on the make
make CFLAGS='blah blah' yourExecutable
Once you start building applications with multiple source modules, it is much better to use a Makefile
. I do find this method convenient for 'one-filers', especially throw-aways that don't need a record of the build recipe.
Get friendly with make
. It is a very useful tool, and the friend of anyone who has to follow up on projects that you build (even yourself).