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Old 03-23-2012, 12:11 PM   #1
kiki strumm3r
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Registered: Feb 2012
Posts: 13

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Using a makefile (with endgame of creating a library)


I am taking a class where my teacher gave us a directory that contains several functions we are going to use (the programming language is Fortran, but I think that is irrelevant to my question). It has a makefile and a readme (see below). I know I could use the 'ar rcs <library name> <list of object modules>' command, but I think the makefile will do that for me with all of the sub-directories. So basically what I want to know is:

1) How do you use a makefile? This isn't really restricted to this particular example because I've seen makefiles while trying to do other things, and I really have no idea how to use them.

2) Will the makefile actually do what I think it will (take all the object modules in the directory and put them into one library)?

3) If I do have to use the ar command and do it manually, do I have to compile all of the files first? Can I use wildcards to do this? (i.e. something like 'gfortran -c ~/src.d/*.d/*.f')

Makefile code:
Code:
LEV1 = frame blas GESS EIGEN util
MAKE =  /bin/make
LIB =	libport3.a

all:;   $(MAKE)  $(LEV1)

$(LEV1):;
	-cd src.d/$@.d; $(MAKE) $@
lib:

install:;

clean:
	rm -f  src.d/blas.d/*.o
	rm -f  src.d/frame.d/*.o
	rm -f  src.d/EIGEN.d/*.o
	rm -f  src.d/GESS.d/*.o
	rm -f  src.d/util.d/*.o
Readme code:
Code:
	makefile: for port3 lib.
	type
		make
src.d
	source directory
examples.d
	SOURCE EXAMPLES IN FORTRAN
 
Old 03-23-2012, 11:10 PM   #2
kiki strumm3r
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Registered: Feb 2012
Posts: 13

Original Poster
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anyone? help?
 
Old 03-24-2012, 12:48 AM   #3
Dark_Helmet
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Registered: Jan 2003
Posts: 2,786

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Here's a link to the GNU Make Manual. Right now, the gnu.org server is not responding... at least through my connection. You may need to wait a while for it to clear up or search for an alternate website.

Also, you need to make sure which make program you are using. GNU make is not the only one floating around. Thought, GNU make will respond to a help invocation with output similar to this:
Code:
user@localhost$ make --version
GNU Make 3.81
Copyright (C) 2006  Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.

This program built for x86_64-pc-linux-gnu
The make manual will answer all your questions in detail, but I'll try to hit all of them in brief.

The make program relies on Makefiles to tell it what to do (most of the time). There are some "implicit" rules that make will default to if the Makefile does not specify everything.

The thing is, make is a tool to automate the software compilation process. In that regard, it's similar to a shell script. Aside from the implicit rules I mentioned earlier, make has no "intelligence" on how to accomplish any specific task: you must explicitly tell it what to do.

You do this by defining "targets." Each target can list individual files as dependencies, other targets as dependencies, or both. After listing the dependencies, you provide instructions to "build" the target.

The strength of make is that the target dependencies describe the relationships between files. Once done, make can "figure out" (a) which instructions need to be performed and (b) the order those instructions need to be performed to "build" a specified target.

For a project that has hundreds of source code files, you don't want to recompile them all when you made a minor change to a single file--you only want to recompile those pieces that depend on the file changed. That's what make brings to the table.
 
  


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