A Makefile is not a shell script. A Makefile has its own variable assignment and substitution syntax.
What is confusing is that the Makefile syntax uses some very similar syntax to bash shell scripts. So it's easy to get them confused.
In the Makefile, you must use $(shell [command]) to tell the make
command to issue a shell command and substitute the output. That's just how it works. See the GNU Make Manual
for all the gory details.
And as a side note, in your example, neither KDIR nor $(shell ...) is a "target." KDIR is a Makefile variable and $(shell ...) is a function call. A target is always defined as "<target name> : <target dependencies>"