While GCC would be involved, you'd need to do this with a Makefile.
Here's a sample Makefile which comes close; however when I tried to use different object sub-directories, it had problems with the definition strings for those sub-directory references. It however does work to compile in the main directory and then from there in the "make install" you can move files to the locations you wish them to be in. Where it ran into trouble was when I tried to say that the objects would be in a sub-directory. The Makefile is like a shell script, but make has more stringent syntax restrictions; for instance those indentations absolutely MUST be TAB characters, not 8 SPACES. So my assumption is that the notations for sub-directories in the view of make must be different from what a bash script accepts. Hope this helps you to get started.
# Sample Makefile
$(GCC) $(CFLAGS) $(DFLAGS) -c $<
$(GCC) $(OBJS) $(LFLAGS) -o wandd
cp -f $(OBJS) $(OBJB)/.
cp -f signed $(IMAGE)/.
rm -f $(OBJB)/*
rm -f $(OBJS)
rm -f $(IMAGE)/signed