Packets loose when i enable the cache
Hello all,
Recently I have been put to a debugging issue as followed. 1. there are 2 PC systems which are connected each other via 2 boards (coldfire cpu 32-bit) in between i.e Quote:
3. The setup is working fine without any faults. But recently it was noticed that the SDRAM cache was not enabled in both the boards (1 and 2) and hence the packet transmission was slow. So, it was required to enable the caches of two boards. 4. Therefore i enabled the caches of two boards by editing the head.s file of the CPU specific code (arch/m68k/coldfire/common/head.S) Code:
#define ACR1_DEFAULT #0x400FA008 /* SDRAM cached/write through */ What might be the reason....It has been a month, M scratching my head....Anyone have idea?? :( |
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