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Old 01-27-2009, 05:32 PM   #1
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pthread_mutex_lock/unlock SMP and CPU cache coherence on core2 SMP


I'm trying to find out how pthread_mutex implementation (on SMP kernels) handles CPU cache coherence issues, specifically which instructions does it use for core2 chips? Is it MFENCE, CPUID, LOCK, etc?
Thanks in advance!


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