I am writing a driver for a PCIe board. This board is configurable through IO memory regions (bars 0 & 1). These bars are exposed to the user space program thanks to the following driver code:
static int BLA_mmap(struct file *pFile, struct vm_area_struct *pVma)
/* -- nResourceStart is the value returned by pci_resource_start -- */
pVma->vm_page_prot = pgprot_noncached(pVma->vm_page_prot);
pVma->vm_flags |= VM_RESERVED | VM_IO;
return remap_pfn_range(pVma, pVma->vm_start, nResourceStart >> PAGE_SHIFT, pVma->vm_end - pVma->vm_start, pVma->vm_page_prot);
Thus, I can access these regions from user space with a simple pointer (after calling mmap):
pBar = 2;
bla = pBar;
My question is about instructions caching. Although pgprot_noncached is used, I wonder if the operations performed through this pointer will be made exactly in the specified order or if any kind of reordering is likely to be performed by the CPU. If reoerdering is performed, is there a standard way to prevent this from happening?
I read Documentation/memory-barriers.txt but I did not find the answer ...
Any help appreciated !