mechanics of mapping process memory addresses to physical addresses on amd64
I'm having difficulty finding out exactly how a memory address as viewed by a process maps to a physical address. I've read about paging, segmentation and poked about in the Intel x86 programmer's manual (vol 1) and AMD's equivalent of the same, but I'm still lacking a clear explanation of exactly how the transition takes place.
When paging is involved I'm close to being happy:
Super-high level overview of address->memory on x86:
1:- The x86 processor has segment registers (all dedicated) and address registers (some dedicated, but often general purpose registers are used).
2:- When a process starts the operating system populates the common segment registers for that process with currently unused segment indices. (I imagine that there is some kind of system call a process can make to ask for more segments.)
3:- Instructions that reference memory provide a segment and an address. (The segment is taken for granted by most instructions, e.g. pop assumes the use of the segment register. However in principle segment registers can be set or segment indices given explicitly. I have not yst used or noticed such an instruction.)
Stage 0: Memory id=(seg index)(address)
4:- When such an instruction is executed the process address is translated to a physical address as follows: (Assuming that the processor is in a mode that uses both paging and segments)
4a:- If the segment has not been used recently an interrupt is called. The operating system is thereby invoked (how?). It looks up the indexed segment, checks that it exists, that
the process is allowed to access it, and if so provides a number which I will call the segment base address.
4b:- The segment base address is added to the address used in the program call.
Stage 1: address=(seg base + address)
4c:- The address is then split into a page address and a page offset. Page accesses work much as segment accesses do: If the page has been recently accessed (def of recently in this context???) a mapping from page index to real address is known and used. Otherwise an interrupt is called and the operating system either provides such a mapping or else calls a page fault.
Stage 2: (page index)(offset)=address
4d:- Finally, once the mapping from page index to physical address is known the physical address can be computed:
Stage 3:- physical address=(physical address of page base)+(offset)
Here's what I don't get:
Segment addressing works for lots of programs because each program doesn't care about the value of the segment indices it uses. It just has a stack segment register and calls an address within that segment. Because each program doesn't care about that, it's possible to have lots of processes addressing the same address without co-ordination because the segment indices that the processes are using are different.
I gather that AMD (and they are not alone) regard segmentation as a silly outdated mechanism and duplication of effort and that only paging should be used. Fair enough, but under these circumstances I'd expect an address still to consist of these three parts:
1:- A prefix that the process doesn't care about; this enables multitasking.
2:- A middle section indicating the page within the context of the process. The process code can have references, e.g. jumps, to addresses that specify the middle section of the address.
3:- An offset within the memory page.
However I don't seem to be able to find reference to this or any other sensible mechanism for use when there are no segments. The descriptions I've encountered are all either so high level as to be meaningless in any real context on else very detailed and technical (good) but don't show how they fit into the big picture.
Do you know how it works, or do you have a reference to a nice mini-essay on the subject?
Last edited by Tischbein; 02-01-2007 at 07:42 PM.