Disabling CPU caches
 

Hi,

I would like to disable the level 1 and level 2 caches of my CPU. I wrote a kernel module to set the 30th bit of the control register cr0. But when I try to insert the module with insmod, the system freezes. I am using a Thinkpad X41 with a Pentium M and kernel 2.6.32-40-generic #87-Ubuntu SMP. What can I do to determine the reason for the freeze?

Thank you for your help!

The code of the module:
And the Makefile:
insmod command:
Edit: Adopted the code of the module, see second post.

As I just found out, the syntax for the mov instruction with control registers is not as I expected: in Intel syntax, the destination register comes first in cases where control registers are involved. I adopted the code of the module in the first post.

However, the overall result stays the same, the system freezes when the module is inserted. I found out that the module runs without problems with this line commented out:
(But it also has no effect because cr0 is not altered.)

Any ideas?

Any suggestions about an other forum where I can ask? Any hint is appreciated, thanks.

You can't disable CPU cache in fly.

Disabling cpu caches gives you a pentium I like processor!!!
The addition of Cache on CPU was one of the best upgrades to cpu architecture and is used to retain temporal data / instructions. as nini09 have said, you cannot disable it at fly, but certain BIOS would give you the option at boot time. Is there any special requirement, or is only homework / test?

It can be done this is from memtest
but you need to flush the cache that's what wbinvd is for.

Thank you for your answers. I want to disable the caches for a research project where we want to measure execution times and want to be sure they are not influenced by the internal caches.

@whizje: I tried your suggestion and apparently, it is working. :) But I have to investigate it further tomorrow when I will have more time.

After some investigation, I found out that the module runs fine (with the corrections from my second post). I just didn't wait long enough after fixing the mov cr0, eax bug, misinterpreating the slow behavior of the system with disabled caches as a complete freeze. My apologies for that.

The code posted by whizje is also working, of course. I didn't find an option for cache disabling in the BIOS of my machine.

Thanks for your input.

how to run the above segment of codes....thanks
 

i am trying to disable the caches ...i want to know how the above code works and how to execute it

@hga Run make and insmod. Source code, makefile and argument for insmod is given in the first post. If you have problems, please ask more specific questions.

can you be more specfic with the steps...where is to be the code saved and with what extension? thank you.

I would suggest to save the source code (in an arbitrary directory) in a file named and the make file in a file named Then run followed by

i saved the above files and tried the make command. But it displays
make: Nothing to be done for `all'..... Can you help me???

---------- Post added 07-31-12 at 07:42 AM ----------

i saved the above files and tried the make command. But it displays
make: Nothing to be done for `all'..... Can you help me???

I have no idea, I have only a very basic knowledge of make...

Hi naam,

It look like your makefile has problem. You can make Hello module work at first and then deal with disableCache.c

Realistically speaking ... and certainly from the point-of-view of any pragmatically useful research project, "internal caches" are the nature of the beast, and therefore any research results must pragmatically consider their influence.

Your handling of this variation should be "appropriate." If you judge that the variation would be significant to your target audience (or to those who seek to validate your results), then you should account for them. (The "execution time" of any algorithm, under real-world conditions, is a confidence interval that is governed by some sort of probability distribution.) If, on the other hand, you judge that it is not, then you should merely report a nominal figure ... "if microseconds actually matter" ... or just the one figure that you have. The presence of caches in all CPUs is well-understood by everyone.

Never report "certainty" where certainty should not be. My brother was once penalized on a test for reporting four digits of precision on a result that only justified three. But then again, that was a situation where the difference was well-known to be an important difference. My brother's error was properly penalized because it was, in fact, an error.

Thank you for your input, sundialsvcs, although I'm not shure wheter I got you right. Actually we wanted to justify our results by showing that a specific timing channel consists both with enabled and disabled caches. Specific execution times were not important for the result, just the fact that a side channel attack was possible.

But since there was to much noise with globally disabled caches, we switched to disable caches for specific processes only. I planed to use the /proc/mttr to set specific memory regions as uncachable but failed with resolving virtual addresses into physical ones. Anyway the project is finished, so I don't know wheter I will continue this work some day.

make file
 

hi ulmo,
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
in the above can you be specific with the "$(shell uname -r)" and the rest ...and also what it is meant and thanks!

I used the files exactly as I posted them; normally you should not need to replace the $(...) parts (they are expanded by the shell). I used bash - don't know if the behavior of other shells differs in this case. Also for the commands, I used them exactly as posted. Did you already tried, rajisekar, or are you asking in advance? It's easier to deal with specific error messages.

make file
 

hi again,
i'm trying to disable the level1 and level2 cache as you did in ubuntu 11.04!

make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules

after running this in the command prompt in "bash shell".. i got the following...

The program 'shell' is currently not installed. You can install it by typing:
sudo apt-get install byobu
PWD: command not found
make: *** /lib/modules//build: No such file or directory. Stop.

P.S:after installing byobu also i got the same :( can you
help me in doing and thanks!

You can simply run without arguments. If this is a misunderstanding because of my statement with the shell, I'm sorry. As I said, I'm no expert with make; I guess ($...) is expanded directly by make, not by the shell.

For the problem with "Nothing to be done for `all'." I think the problem are space characters instead of a tab character at the beginning of the line with "make -C". For me it only works with a tab.

The presence of a side-channel attack would have to be demonstrated in the presence of known CPU caching behavior, not at the exclusion of it. The exploitable characteristic of the system must be sufficiently pronounced that any and all cache-induced variances (CPU or otherwise) do not prevent a useful exploit. Disabling caches would perhaps further demonstrate the flaw, but in doing so they create conditions that are no longer quite real-world. If a side-channel is there, then presumably the caches would not very seriously affect it, because the exploited behavior would lie well outside the zone of uncertainty produced by the cache's known hit-probability distributions.

disable cache
 

hi ulmo,
Thanks a lot! you were right! at last, it worked with "make" command and your "tab" part:) Thanks a lot again :) and as you said i could see my system get freezes.

You are absolutely right. That's why our experiments without caches were meant to strengthen our assumption that the timing channel was not caused by caches. This was important to us because we wanted to separate from cache based timing attacks.
Disabling CPU caches seemed to us as the most straightforward way. I have no experience with prediction of cache behavior, but I would assume this to be difficult because we were analyzing a Java virtual machine (where I would assume some code running in between I can not predict). But maybe that's an option if the project gets resumed.

Disabling cache
 

hi ulmo,
could you tell me how it is working like setting 30th bit of control register is enough to disable the cache?if so and in what way?As you have mentioned earlier the system get freezes after executing the line mov cr0,eax ? is it so?

For me it seemed to be enough, but Intel's documentation says you have to disable MTRRs also. See Intel 64 and IA-32 Architectures Software Developer’s Manual volume 3 chapter 11.5.3 (http://www.intel.com/content/www/us/...-manuals.html/). In linux disabling MTRRs is also possible by executing as root something like See http://www.mjmwired.net/kernel/Documentation/mtrr.txt With an X server running it seemed to me the system was freezed, but it was not. Without X it was possible for me to work with the system, although the console prints only a few lines (something like three) per second.

disabling cache
 

hi ulmo,
how can you prove that the L1 and L2 caches get disabled? we cannot say that the system get freezes which means the cache got disabled! Let me know is there any tester to prove the above ?! or any other idea ?? Between do you have any idea for disabling the hyper threading ?? thanks :)

Unfortunately I don't know how to do this. As I described, I experienced a significant performance drop, even without X (which is of course no prove). I would rely on the Intel specification to derive the state of internal caches from cr0.
I'm afraid I have no experience with hyper threading so I don't know about it.

Hi folks,
I also have to disable/enable the cpu caches for a research project. Disabling caches by setting bit 30 in %cr0 works fine. One can verify the absence of the caches with a small test program like this (cachetest.c):

and profile it using the linux perf tool like:
The memory array fits into the cache and you should get a low number for the L1 cache misses. For me it is about 10000 misses where most of the misses come from the dynamic loader.
When I disable the caches the number goes up to something like 8 million misses. The execution time is about 1000x higher with the caches disabled.
When I reset bit 30 in %cr0 the number of misses drops back to about 10000 and the test program runs at the original execution time.

However, the system is still horribly slow. Much faster then having the caches disabled but still very slow until I restart the system.

Could there be some side effects I'm missing here? I checked the contests of %cr0 and it is the same as after startup. Any ideas?

Thanks!

I used the code from the first post and it seems to disable caches only on one CPU core.
I have an Intel i5-2320 (4 cores) and after inserting the module, some executions of programs run slow (about 10 times slower than normally), but some equally fast as before. (that is the same program run several times sometimes runs fast as before, sometimes 10 times slower)
The system monitor (I use Ubuntu 14.04) shows one CPU core almost always 100% loaded, while others much less.

Can anyone shed some light onto this?

Also, the code apparently works only in 32 bit mode. It wont even compile with -m64 option.

Just a note: the MTRR method works fine (system is 100 times slower, I did not check any details, is there a good tool to detect caches?) on both 32 and 64 bit systems.

First run:
to get a list of regions. The one or few segments that add up to the size of RAM are the correct ones to disable (on my system there were 00: 2GB, 01: 1GB and 02: 1GB).

Then run for each segment:
(replace 00 with the segment number)

Thanks for posting your solution, xerces8. Unfortunately, I don't know of any tool to detect the presence of caches.