I am not clear about the address of gdtr.

from the book "Understanding The Linux Kernel". 2.2.2 Segment Descriptor( page 38)

"The address of the GDT in main memory is contained in the gdtr processor register and the address of the currently used LDT is contained in the ldtr processor egister."

My question: is the address in gdtr logical address/linear address or physical address?

I think it should be physical address, because paging has not implemented before that. Need someone help to confirm it and provide better explanation

Another question about paragraph: book "Understanding The Linux Kernel". 2.2.4 Segment Linux (page 43).

For each process, therefore, the GDT contains two different Segment Descriptors: one for the TSS segment and one for the LDT segment. The maximum number of entries allowed in the GDT is 12+2xNR_TASKS, where, in turn, NR_TASKS denotes the maximum number of processes.where, in turn, NR_TASKS denotes the maximum number of processes. In the previous list we described the six main Segment Descriptors used by Linux. Four additional Segment Descriptors cover Advanced Power Management (APM) features, and four entries of the GDT are left unused, for a grand total of 14.

12+2xNR TASKS, where does the 12 come from? I think it should be 14 as "In the previous list we described the six main Segment Descriptors used by Linux. Four additional Segment Descriptors cover Advanced Power Management (APM) features, and four entries of the GDT are left unused, for a grand total of 14."

I might misunderstand something, please help to make me clear.

Thanks, $XSM

Read x86 pentium intel manuals for reference.

Osdev site has also page on it.

2.4.1 Global Descriptor Table Register (GDTR)
The GDTR register holds the base address (32 bits in protected mode; 64 bits in
IA-32e mode) and the 16-bit table limit for the GDT. The base address specifies the
linear address of byte 0 of the GDT; the table limit specifies the number of bytes in
the table.
The LGDT and SGDT instructions load and store the GDTR register, respectively. On
power up or reset of the processor, the base address is set to the default value of 0
and the limit is set to 0FFFFH. A new base address must be loaded into the GDTR as
part of the processor initialization process for protected-mode operation.
See also: Section 3.5.1, Segment Descriptor Tables.

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so it should be linear address of the 0 of GDT.
how could the linear address to be translate to physical address?