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Old 09-14-2015, 03:04 PM   #1
ballsystemlord
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What should I set march to


I know, look at the cpuinfo.
I have an Intel 2117U processor:
http://ark.intel.com/products/71469/...Cache-1_80-GHz
https://en.wikipedia.org/wiki/Ivy_Br...rchitecture%29
It's an Ivy-bridge, no question, the NM is right, the wattage is right, the year is right, but it does not support all the ivy-bridge instructions (like AVX), the instructions it supports makes it llok like the nehalem arch.
Currently, I have march set to "native", but distcc will not like "native" (native == x86-64) and the only other one I can use that would make sense is plain old "x86-64".
I'm using gentoo and some programs don't like the processor set to x86-64.
So, my question is, should I submit a bug report to the gcc devs or am I missing siomething (hoping it's the latter)?
Cpuinfo here: http://dpaste.com/2BXSZ18

Last edited by ballsystemlord; 09-14-2015 at 03:06 PM. Reason: Adding link for cpuinfo
 
Old 09-15-2015, 09:52 AM   #2
cepheus11
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Gentoo has the package "app-misc/resolve-march-native". It contains the program:

Code:
$ resolve-march-native

-march=ivybridge -mno-aes -mno-avx -mno-cx16 -mno-f16c -mno-fsgsbase -mno-pclmul -mno-popcnt -mno-rdrnd -mno-sse4
 -mno-sse4.1 -mno-sse4.2 -mno-xsave -mno-xsaveopt --param l1-cache-line-size=64 --param l1-cache-size=32
 --param l2-cache-size=6144
(This is from a virtualbox guest in win7 on a Core i5)
 
Old 09-15-2015, 10:10 AM   #3
/dev/random
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If you are missing features it's safer to use the nehalem arch. I had a few AMD's that were set to K8 arch even if they were newer because they didn't support some instructions the FX did even through it was a first gen FX. I would go with nehalem arch if your cpu is lacking features, just to play it safe.
 
Old 09-22-2015, 02:23 PM   #4
ballsystemlord
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Ok, the resolve program says my system is a core-avx-i, Intel claims that its an ivybridge, and this small script from https://wiki.gentoo.org/wiki/Distcc says its a plain x86_64. Interesting.
Code:
gcc -v -E -x c -march=native -mtune=native - < /dev/null 2>&1 | grep cc1 | perl -pe 's/ -mno-\S+//g; s/^.* - //g;'
I would just set it to nehalem, but I'm concerned that it might enable optimizations that are specific to that processor chip (I have heard of such things). The other script a bit further down on the previously mentioned page gives no output.
Tell me, if my system supports avx instructions what would the cpuinfo say. I'm asking because there is nothing specifically mentioning avx in the name of any of them.
It would also be helpful if there is anyone out there who could paste a copy of their cpuinfo if they have an ivybridge processor, it would give me something to work from.
 
Old 09-22-2015, 02:33 PM   #5
/dev/random
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Quote:
Originally Posted by ballsystemlord View Post
Ok, the resolve program says my system is a core-avx-i, Intel claims that its an ivybridge, and this small script from https://wiki.gentoo.org/wiki/Distcc says its a plain x86_64. Interesting.
Code:
gcc -v -E -x c -march=native -mtune=native - < /dev/null 2>&1 | grep cc1 | perl -pe 's/ -mno-\S+//g; s/^.* - //g;'
I would just set it to nehalem, but I'm concerned that it might enable optimizations that are specific to that processor chip (I have heard of such things). The other script a bit further down on the previously mentioned page gives no output.
Tell me, if my system supports avx instructions what would the cpuinfo say. I'm asking because there is nothing specifically mentioning avx in the name of any of them.
It would also be helpful if there is anyone out there who could paste a copy of their cpuinfo if they have an ivybridge processor, it would give me something to work from.
If your cat /proc/cpuinfo is not showing that the the avx instruction is supported, linux will not use said instructions.

Can you give us the full output of cpuinfo?

Last edited by /dev/random; 09-22-2015 at 02:37 PM.
 
Old 09-25-2015, 10:20 AM   #6
ballsystemlord
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There are two cores, I'm only posting data on one because they are identical.
Code:
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 58
model name	: Intel(R) Pentium(R) CPU 2117U @ 1.80GHz
stepping	: 9
microcode	: 0x1b
cpu MHz		: 1800.000
cache size	: 2048 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 2
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 13
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer xsave lahf_lm arat epb pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase smep erms xsaveopt
bugs		:
bogomips	: 3591.52
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:
 
Old 09-25-2015, 01:12 PM   #7
/dev/random
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Quote:
Originally Posted by ballsystemlord View Post
There are two cores, I'm only posting data on one because they are identical.
Code:
processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 58
model name	: Intel(R) Pentium(R) CPU 2117U @ 1.80GHz
stepping	: 9
microcode	: 0x1b
cpu MHz		: 1800.000
cache size	: 2048 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 2
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 13
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx rdtscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf eagerfpu pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic popcnt tsc_deadline_timer xsave lahf_lm arat epb pln pts dtherm tpr_shadow vnmi flexpriority ept vpid fsgsbase smep erms xsaveopt
bugs		:
bogomips	: 3591.52
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:
Use nehalem

According to this your mobile CPU also doesn't support the AES instruction either.

https://gcc.gnu.org/onlinedocs/gcc-5...ml#x86-Options

Last edited by /dev/random; 09-25-2015 at 01:14 PM.
 
  


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