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[root@localhost ~]# cpuid -i
CPU 0:
vendor_id = "GenuineIntel"
version information (1/eax):
processor type = primary processor (0)
family = Intel Pentium 4/Pentium D/Pentium Extreme Edition/Celeron/Xeon/Xeon MP/Itanium2, AMD Athlon 64/Athlon XP-M/Opteron/Sempron/Turion (15)
model = 0x4 (4)
stepping id = 0x3 (3)
extended family = 0x0 (0)
extended model = 0x0 (0)
(simple synth) = Intel Pentium 4 (Prescott N0) / Xeon (Nocona N0 / Irwindale N0), 90nm
miscellaneous (1/ebx):
process local APIC physical ID = 0x0 (0)
cpu count = 0x2 (2)
CLFLUSH line size = 0x8 (8)
brand index = 0x0 (0)
brand id = 0x00 (0): unknown
feature information (1/edx):
x87 FPU on chip = true
virtual-8086 mode enhancement = true
debugging extensions = true
page size extensions = true
time stamp counter = true
RDMSR and WRMSR support = true
physical address extensions = true
machine check exception = true
CMPXCHG8B inst. = true
APIC on chip = true
SYSENTER and SYSEXIT = true
memory type range registers = true
PTE global bit = true
machine check architecture = true
conditional move/compare instruction = true
page attribute table = true
page size extension = true
processor serial number = false
CLFLUSH instruction = true
debug store = true
thermal monitor and clock ctrl = true
MMX Technology = true
FXSAVE/FXRSTOR = true
SSE extensions = true
SSE2 extensions = true
self snoop = true
hyper-threading / multi-core supported = true
therm. monitor = true
IA64 = false
pending break event = true
feature information (1/ecx):
PNI/SSE3: Prescott New Instructions = true
MONITOR/MWAIT = true
CPL-qualified debug store = true
VMX: virtual machine extensions = false
Enhanced Intel SpeedStep Technology = true
thermal monitor 2 = false
context ID: adaptive or shared L1 data = true
cmpxchg16b available = true
xTPR disable = true
cache and TLB information (2):
0x50: instruction TLB: 4K & 2M/4M pages, 64 entries
0x5b: data TLB: 4K & 4M pages, 64 entries
0x60: L1 data cache: 16K, 8-way, 64 byte lines
0x40: No L3 cache
0x70: Trace cache: 12K-uop, 8-way
0x7d: L2 cache: 2M, 8-way, sectored, 64 byte lines
processor serial number: 0000-0F43-0000-0000-0000-0000
deterministic cache parameters (4):
cache type = no more caches (0)
cache level = 0x0 (0)
self-initializing cache level = false
fully associative cache = false
extra threads sharing this cache = 0x0 (0)
extra processor cores on this die = 0x0 (0)
system coherency line size = 0x0 (0)
physical line partitions = 0x0 (0)
ways of associativity = 0x0 (0)
number of sets - 1 (s) = 0
MONITOR/MWAIT (5):
smallest monitor-line size (bytes) = 0x40 (64)
largest monitor-line size (bytes) = 0x40 (64)
enum of Monitor-MWAIT exts supported = false
supports intrs as break-event for MWAIT = false
number of C0 sub C-states using MWAIT = 0x0 (0)
number of C1 sub C-states using MWAIT = 0x0 (0)
number of C2 sub C-states using MWAIT = 0x0 (0)
number of C3 sub C-states using MWAIT = 0x0 (0)
number of C4 sub C-states using MWAIT = 0x0 (0)
extended feature flags (0x80000001/edx):
SYSCALL and SYSRET instructions = false
execution disable = true
64-bit extensions technology available = true
Intel feature flags (0x80000001/ecx):
LAHF/SAHF supported in 64-bit mode = false
brand = " Intel(R) Pentium(R) 4 CPU 3.00GHz"
L1 TLB/cache information: 2M/4M pages & L1 TLB (0x80000005/eax):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 TLB/cache information: 4K pages & L1 TLB (0x80000005/ebx):
instruction # entries = 0x0 (0)
instruction associativity = 0x0 (0)
data # entries = 0x0 (0)
data associativity = 0x0 (0)
L1 data cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (Kb) = 0x0 (0)
L1 instruction cache information (0x80000005/ecx):
line size (bytes) = 0x0 (0)
lines per tag = 0x0 (0)
associativity = 0x0 (0)
size (Kb) = 0x0 (0)
L2 TLB/cache information: 2M/4M pages & L2 TLB (0x80000006/eax):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):
instruction # entries = 0x0 (0)
instruction associativity = L2 off (0)
data # entries = 0x0 (0)
data associativity = L2 off (0)
L2 unified cache information (0x80000006/ecx):
line size (bytes) = 0x40 (64)
lines per tag = 0x0 (0)
associativity = 8-way (6)
size (Kb) = 0x800 (2048)
Advanced Power Management Features (0x80000007/edx):
temperature sensing diode = 0x0 (0)
frequency ID (FID) control = 0x0 (0)
voltage ID (VID) control = 0x0 (0)
thermal trip (TTP) = 0x0 (0)
thermal monitor (TM) = 0x0 (0)
software thermal control (STC) = 0x0 (0)
TscInvariant = 0x0 (0)
Physical Address and Linear Address Size (0x80000008/eax):
maximum physical address = 0x24 (36)
maximum linear address = 0x30 (48)
Logical CPU cores (0x80000008/ecx):
number of logical CPU cores - 1 = 0x0 (0)
ApicIdCoreIdSize = 0x0 (0)
(multi-processing synth): hyper-threaded (t=2)
(synth) = Intel Pentium 4 (Prescott N0), 90nm
I look at all that with little comprehension, but the last line gives me enough info to clearly identify my processor as the P4 630 as that is the only Prescott model with 2MB cache.
That Wikipedia page also concurs with this conclusion.
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