Hi, a process is trying one access to memory, for example through an array (ex.: vect[0]=123. What happens?
Here below what I guess but I'm not sure and accept any comment (please, distinguish between "the system" and "the CPU" in case).
Let's suppose swapping to disk disbled.
We have two scenarios: without and with cache.

If no cache is present in the system:
1. The CPU must discover the phys addr of vect[0] virtual addr. To do that, has to read from 3 (or 2 depending on the system?) pages tables, stored in memory as well.
2. The CPU writes to the final address.
These mean 4 memory accesses.

If cache is present:
1. Like above but, if the pages tables are in cache, we have 3 accesses to that.
2. If the req. page is not in cache, it's reads from ram and transferred to it. Afterwards, cache is written.
In the best case we have 4 cache accesses.

Best regards
Pupillo

You apparently don't know about the TLB, another cache-like thing that remembers complete translations.

So most often, the CPU finds the complete translation (virtual address to physical address) with one TLB access.

Yes, there is the TLB, but I didn't realized that it's an associative memory; I thought it was very fast but the CPU had to walk through its entries searching for that virtual address (or better virtual page start address). I knew that the TLB has very few entries.
Thanks
Tommaso