It is possible to simply use wildcards in a makefile to tell it to compile all the .c files. The problem is that the whole idea of a makefile is to list dependencies and only recompile parts that depend on things that changed. The dependencies for a .c file aren't simply the .c file itself. You need to list its include files too.
Fortunately, gcc has a -M option to auto generate makefiles. It will correctly identify the include file dependencies. If you follow the directions in the GNU make manual section 4.14
, you'll get a makefile that includes other autogenerated makefiles. This means that your main makefile will never change.
Everytime I've used those instructions, I get a makefile that will produce a harmless error the first time it's run (because the submakefiles don't exist yet, and it generates them). I think it would work better if you compromised and allowed your makefile to change. Then you could just run this:
gcc -M *.c > Makefile; make -f Makefile
You could even put that in a script.