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I use USART0 and USART1 of AT91RM9200 to send and receive data packets of variable length (typical 513 bytes). Each USART is set to 485 mode and baud rate is 250K. Between the data packets is a break of approximately 112 microseconds. USART is set to interrupt on receiving breaks. DMA is used for data transfer. When USART interrupts on receiving a break (RXBRK), the ISR reads DMA data counter to mark the beginning of a new packet in the DMA buffer, and then transfers the data of the packet just received from DMA buffer to device buffer.
The problem I have now is that from time to time when RXBRK interrupt comes and the ISR reads DMA counter ATMEL_PDC_RCR, the counter value is already 1 byte beyond the beginning of the packet. It looks like the RXBRK interrupt is not serviced quickly enough and the DMA already transfer the byte following the break into the DMA buffer when the ISR is invoked.
When both USART0 and USART1 are receiving packets, the problem gets worse than when only one port is receiving. Adding system load (like running a web server) also causes more packets missing their first byte.
Would you please give some pointers on what might cause the delay and how to correct it? Thank you!
Always one byte? That's strange. A bit is 4 microseconds, so a byte is 32-40 depending on your settings.
Sounds to me like you are getting the break interrupt at the end of the break, after the first character of the next packet has already started coming in. Then you only have one byte time to process it and sometimes you don't make it. Just a guess, and no idea how to fix it.